1. Field
This invention relates generally to electronic circuits and more particularly to a master-slave flip-flop.
2. Related Art
Flip-flops are typically used for storing a single bit of data. One type of flip-flop is a master-slave flip-flop. A master-slave flip-flop (MSFF) includes two storage elements, or latches, operating in series.
An input terminal of a MSFF may be coupled to an output terminal of a circuit that provides dynamically changing digital data to the MSFF. The circuit that provides the dynamically changing digital data may be a memory. The memory may include a plurality of bitcells and at least one sense amplifier with an output node of a sense amplifier coupled to an input terminal of the MSFF. A setup time of the MSFF is a factor that should be considered when inputting data to the MSFF.
A setup time of a flip-flop is the minimum amount of time an input signal should be held steady before a clock event so that the input data is reliably sampled. A hold time of a flip-flop is the minimum amount of time the input signal should be held steady after the clock event so that the input signal is reliably sampled. A clock-to-Q launch delay of a flip-flop is an interval between occurrence of the clock event and occurrence of an output signal, at an output terminal of the flip-flop, representative of a state of an input signal at the clock event. A clock-to-Dout launch delay of a MSFF is an interval between occurrence of the clock event and occurrence of an output signal, at an output terminal of the MSFF, the output being representative of a state of an input signal at the clock event. A datain-to-dataout lag of a MSFF is equal to a setup delay plus a launch delay, where the setup delay is Din-to-clock, and the launch delay is clock-to-Dout.
When a wordline and a bitline of a memory are selected, a differential voltage outputted by a selected bitcell increases with time. A value of such differential voltage is dependent, in part, on duration that the bitline is asserted, and, in part on strength of the bitcell. The sense amplifier is a high gain amplifier which, when enabled, amplifies the differential voltage outputted by the bitcell. A value of such amplified differential voltage is dependent, in part, on duration of an interval between when the bitline is asserted and when a sense enable signal is asserted, and, in part, on a gain of the sense amplifier. The amplified differential voltage may be outputted by the sense amplifier to a MSFF. Determination of data out of the memory depends on detection by the MSFF of the value of the amplified differential voltage outputted by the sense amplifier. If data out of the memory is required to arrive earlier, i.e., if detection by the MSFF is desired to occur sooner, then two known options are available: 1) use a larger, i.e., stronger, bitcell, but this option disadvantageously results in more area and more power consumption, and 2) reduce a detection threshold for the differential voltage that appears at an input of the sense amplifier, but this option disadvantageously increases a possibility of a read failure.